Jiawen Wu
Computer Engineering,
Texas A&M University
Fingers Crossed
About Me
Hi there! This is Jiawen's homepage.

My research interests fall into the fields of VLSI Design and Computer Architecture, especially Hardware Accelerator, Hardware Security, and their intersections.

I'll be joining SETH lab led by Prof. Jeyavijayan “JV” Rajendran at Texas A&M 2023 fall.
Research
Sparse Neural Network Hardware Accelerator Design
School of Microelectronics, Tianjin University
Post-Quantum Cryptography NTT Hardware Accelerator
State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Automatic Management of Devices for Robotic Applications
Department of Computer Science, The University of Hong Kong
The Analysis of Data Center Network Congestion Control Solution
School of Microelectronics, Tianjin University
Blog
Image classificaton using a hybrid of ResNet 50 and GhostNet
Measuring body temperature with face recognition
An Approach to License Plate Recognition System on FPGA
A ResNet18 image classificaton with ROS2 in Docker
The final homework for class Modern Programing Techniques
A blockchain project on web using Ethereum Rinkeby test network
Minted my own NFTs on OpenSea
Contact
Email
Linkedin
Google Scholar
Github