Hi there! This is Jiawen's homepage.

My research interests fall into the fields of VLSI Design and Computer Architecture, especially Hardware Accelerator, Hardware Security, and their intersections. Especially on Zero-Knowledge Proofs Hardware.

I'm in SETH lab led by Prof. Jeyavijayan “JV” Rajendran at Texas A&M from 2023. Prior to that, I received my B.S. degree in Electrical Engineering from Tianjin University, China in 2023.

Impact Statement: I am passionate about designing efficient and secure hardware accelerators for emerging applications, such as machine learning, cryptography, and blockchain. And make the world a better place.