Research
Sparse Neural Network Hardware Accelerator Design
School of Microelectronics, Tianjin University
Post-Quantum Cryptography NTT Hardware Accelerator
State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Automatic Management of Devices for Robotic Applications
Department of Computer Science, The University of Hong Kong
The Analysis of Data Center Network Congestion Control Solution
School of Microelectronics, Tianjin University
Publications
ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM
Ku, Jonathan, Junyao Zhang, Haoxuan Shan, Saichand Samudrala, Jiawen Wu, Qilin Zheng, Ziru Li, JV Rajendran, and Yiran Chen. "ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM." ArXiv, (2024). Accessed June 6, 2024. /abs/2402.14152.
Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array
Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li. 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)
PFDCT: An Enhanced Transport Layer Protocol for Precise Flow Control in Data Centers
Zhuo Li, Huiyan Wang, Xiangdong Yi, Xinyi Zhang, Jiawen Wu, Yubin Zhang, Peng Luo, Kaihua Liu. Electronics 12 (8), 1890
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